FIG. 1 shows a conventional M/N type clock frequency synthesizer 10. In the context of the present application, an “M/N type” clock frequency synthesizer is one in which (i) a reference clock signal frequency is divided before it is input into a phase or phase-frequency detector, and (ii) an oscillator output is divided before it is input into the phase or phase-frequency detector. M/N type clock frequency synthesizer 10 generally comprises a divider 12 receiving a reference clock signal having a frequency fref and providing a signal having a frequency fref/N, a phase-frequency detector 14, a charge pump 16, a filter 18, a voltage controlled oscillator (VCO) 20 providing an output clock signal having a frequency fvco, and a divider 22. Dividers 12 and 22 respectively receive configuration signals N[0: (n−1)] and M[0: (m−1)], where N and M are the respective factors by which dividers 12 and 22 divide their respective input signals, and n and m are the respective widths of the configuration signals. Except for the divider 12, the remainder of clock frequency synthesizer 10 is known as a phase locked loop (PLL).
FIG. 2 shows a conventional second-order filter 18, comprising a resistor 40 and a first capacitor 42 in series, and parallel thereto a second capacitor 44. Filter 18 provides a wave-or signal-smoothing function on the output current UP/DN of charge pump 16 to provide a frequency control signal CONTROL to VCO 20. Resistor 40 and second capacitor 44 are coupled to the UP/DN node, and first capacitor 42 and second capacitor 44 are coupled to a ground potential or voltage level. In the embodiment shown in FIG. 2, the UP/DN node is also directly coupled to filter output CONTROL that is input into VCO 20 to adjust or control the current injected into VCO 20, and/or a bias and/or voltage applied to stages of VCO 20.
A common problem that clock frequency synthesizer designers face is how to maintain stability of the PLL over a wide range of frequencies. In a conventional M/N type frequency synthesizer, it is also advantageous to keep the loop bandwidth at least about ten times less than fref/N. At that multiple, a continuous time approximation can be used to model the PLL, and the PLL stability can be maintained relatively easily.
Loop bandwidth generally satisfies the equation fc=(I/2π)·R·(kvco/M), where fc is the loop bandwidth, I is the charge pump current, R is the resistance of resistor 40, kvco is the voltage-to-frequency gain of VCO 20, and M is the factor by which divide module 22 divides the VCO output signal 24. The VCO gain kvco generally satisfies the equation kvco=Δ(fvco)/Δ(V), where V is the control voltage for the VCO, and fvco=(M/N)·fref.
In many applications, it is desirable to keep fref/N constant, primarily to simplify the PLL design, but also in part to support and maintain the stability of the PLL. In those applications where fref may vary or change, it is conventional to change the factor N by which divider 12 divides fref to try to keep fref/N constant. However, there are also applications where fvco may change. In addition, a seller, designer and/or manufacturer of a PLL-containing integrated circuit (IC) may wish to use a single design and/or IC in multiple applications covering a range of fvco values. In such cases, the loop stability can be maintained if one is able to keep the loop bandwidth fixed or essentially constant.
The factor M of feedback divider 22 may vary widely when the VCO 20 operates over a large frequency range. Unfortunately for the designer of a PLL operating over a wide frequency range, feedback divider factor M is in the denominator of the loop bandwidth equation. As a result, changing M has a non-linear, and sometimes dramatic, effect on the corresponding change on the loop bandwidth. This can make it challenging to keep the loop bandwidth fixed over a wide VCO frequency range, and thus, maintain PLL stability over a wide VCO frequency range.
One way designers attempt to control the loop bandwidth function is to control the charge pump current such that (I/M) is a constant value. As a result, when the operable frequency range of the VCO is sufficiently large, designing a charge pump that accurately controls both large and small currents (as well as both large and small changes in currents) can be difficult and/or complicated.
Another approach to addressing this difficulty has been to control resistance and capacitance values in filter 18. In some implementations, switches are placed at inputs to the filter 18 to select from among a group of different resistors and/or capacitors. However, use of such switches tends to introduce noise into the VCO, which can degrade PLL performance.
Therefore, a need exists to control VCO gain over a wide frequency range in a predictable and controllable manner. Ideally, designers seek a technique for making VCO gain a linear function of VCO frequency, without complicated charge pump designs and/or complicated schemes for switching different components into and/or out of noise-sensitive parts of the PLL circuitry.